Breaking Rent’s Rule: Opportunities for 3d Interconnect Networks

Stochastic estimates of wire-length based on Rent’s rule predict a benefit of 3D integration over traditional ICs, tapering off with a 50% reduction for 8 tiers. However, Rent’s rule is unnecessarily pessimistic, because it assumes an extrapolation of architectures that were conceived in two dimensions. This paper examines the gains possible in several 3D interconnect network topologies. Placement experiments with a 64-node 3-cube network show that a 75% reduction is possible with 4 tiers, and larger gains are possible with larger networks. Architectures for systems limited by nearest-neighbor communication are discussed, which are likely to show the most benefit from 3D integration. INTRODUCTION 3D Integration is becoming more common, driven not by the need for more speed or less power, but rather greater density. One of the greatest selling points for 3D ICs today is that it is one of the only ways known to meet the demand for increased transistor density on a chip, while still getting a sufficient returnon-investment for lithography equipment for technology nodes smaller than 45nm. As a result, there have been more announcements of commercial 3D processes, such as the 3D memory announced by Samsung in April of this year [1]. The expected availability of this technology creates an exciting opportunity to explore new architectures that take advantage of the third dimension. Most of the research on the expected benefits of 3D processing has focused on stochastic Rent’s Rule analyses of interconnect. These studies show that the longest wires will shorten by approximately tiers N when the first few tiers are added, but that the benefit drops off with increasing tiers, giving about half of the length when you have 8 tiers [2,3,4]. This finding suggests that today’s interconnectdominated digital systems could show a performance improvement of up to 2X from 3D integration, roughly two process generations of improvement. But is a 2X improvement the best that we can do? Stochastic Rent’s-Rule-based analyses assume an extrapolation of trends observed in existing 2D chips, namely random-logic in microprocessors [5]. They will therefore show us an accurate idea of how a 2D design will perform when mapped into 3D. But designs conceived in 3D and mapped into 2D will show a different trend. The goal of this paper is to explore these trends for the application of 3D interconnection networks to see if greater improvements are possible than previously predicted. The paper begins with an introduction to previous work in interconnection networks, followed by a discussion of the placement algorithm used to study interconnect lengths. Experimental results on representative interconnection networks are then shown, followed by predictions of the architectures that are likely to show disproportionately large benefit from 3D integration. SOC INTERCONNECTION NETWORKS Interconnection networks have primarily been an area of interest in computer architecture, but are also of interest to VLSI designers, due to the heavy use of interconnect fabrics in multi-processor Systems-onChip. As shrinking devices enable us to build more complicated systems, wires behave as if they were proportionately longer, making communication between the increased number of functional units a bigger issue. In most SoCs, it is essential to link the components via a central interconnect network. Dally and Towles [6] advocate SoC design via a modular approach in which functional units do not communicate via global dedicated wires, but over a central interconnection network. They propose creating chips of regular tiles, where each tile contains a function-unit and a router to communicate with other tiles. In [7], Heo and Asanović focus on the global interconnect issues of today’s chips from a power consumption standpoint, comparing the power difference between dedicated wires for global interconnections to a centralized interconnection network. Through wire delay and power consumption models, they show that power consumption is minimized for a tile size of 2mm in a 70nm technology. Ye and De Micheli [8] discuss the importance of carefully considering the placement of functional units in an SoC, and that microprocessor SoC floorplanning and ASIC floorplanning have fundamentally different goals. Unlike ASICs, it is typically valid to assume that interconnection networks are connected in regular structures and have uniform function-units. While ASIC floorplanning is more concerned with point to point connections, a balanced and uniform placement that results in uniform wire lengths is important in an interconnection network to help keep down the expected network latency. This difference is so severe that the authors experience up to 6.5 time improvements when using their microprocessor SoC floorplanning tool versus using a standard ASIC floorplanning tool. The authors use the quadratic placement algorithm as a florrplanning tool for various interconnect networks to search for similar improvements for networks-on-chip. Here, we apply their approach to 3D networks-on-chip. QUADRATIC PLACEMENT ALGORITHM In cell placement, we cannot guarantee an optimal placement to minimize wiring cost, but the quadratic placement algorithm [9] is generally accepted as a simple algorithm that yields a good solution. The drawback to this algorithm is that it only works best for a relatively few number of objects, as calculating eigenvectors for large matrices gets to be a computationally intensive task. The algorithm assumes that there exists the abstract problem of placing a relatively small number of points (each with area or volume equal to zero) in continuous r-dimensional Euclidean space. The connectivity of the rdimensional graph consisting of the set of objects M = {m1, m2,..., mp}, is given by the p × p matrix C, where cij is determined according to: • cij = 0 if mi and mj are not connected and i ≠ j • cij = wij > 0 where wij is the weighting coefficient between objects mi and mj if they are connected and i ≠ j • cij = ∑ ≠ = − p i k k ik w , 1 when i = j We assume that there are a total of p objects to place, therefore we must find the set of coordinate vectors (x1,y1,z1), (x2,y2,z2),..., (xp,yp,zp) such that we minimize the weighted sum of squared distances between all connected points. This objective function corresponds to the wiring cost of a circuit if the coordinate vectors are interpreted as cell placements in the circuit. It is shown for three dimensions in (1): ( ) ( ) ( ) ( ) ( ) z C z y C y x C x z z y y x x c z y x T T T p